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  <titleInfo>
    <nonSort>The </nonSort>
    <title>design warrior's guide to FPGAs</title>
    <subTitle>devices, tools and flows</subTitle>
  </titleInfo>
  <name type="personal">
    <namePart>Maxfield, Clive</namePart>
    <namePart type="date">1957-</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
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  <typeOfResource>text</typeOfResource>
  <genre authority="">Matériel didactique.</genre>
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    <place>
      <placeTerm type="text">Amsterdam</placeTerm>
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    <publisher>Newnes/Elsevier</publisher>
    <dateIssued>c2004</dateIssued>
    <dateIssued encoding="marc">2004</dateIssued>
    <issuance>monographic</issuance>
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  <language>
    <languageTerm authority="iso639-2b" type="code">eng</languageTerm>
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  <physicalDescription>
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    <extent>xvi, 542 p. : ill. ; 24 cm. + 1 cédérom (12 cm.)</extent>
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  <tableOfContents>Ch. 1. Introduction -- Ch. 2. Fundamental concepts -- Ch. 3. The origin of FPGAs -- Ch. 4. Alternative FPGA architectures -- Ch. 5. Programming (configuring) an FPGA -- Ch. 6. Who are all the players? -- Ch. 7. FPGA versus ASIC design styles -- Ch. 8. Schematic-based design flows -- Ch. 9. HDL-based design flows -- Ch. 10. Silicon virtual prototyping for FPGAs -- Ch. 11. C/C++ etc.-based design flows -- Ch. 12. DSP-based design flows -- Ch. 13. Embedded processor-based design flows -- Ch. 14. Modular and incremental design -- Ch. 15. High-speed design and other PCB considerations -- Ch. 16. Observing internal nodes in an FPGA -- Ch. 17. Intellectual property -- Ch. 18. Migrating ASIC designs to FPGAs and vice versa -- Ch. 19. Simulation, synthesis, verification, etc. design tools -- Ch. 20. Choosing the right device -- Ch. 21. Gigabit transceivers -- Ch. 22. Reconfigurable computing -- Ch. 23. Field-programmable node arrays -- Ch. 24. Independent design tools -- Ch. 25. Creating an open-source-based design flow -- Ch. 26. Future FPGA developments -- App. A. Signal integrity 101 -- App. B. Deep-submicron delay effects 101 -- App. C. Linear feedback shift registers 101.</tableOfContents>
  <note type="statement of responsibility">Clive "Max" Maxfield.</note>
  <note>Comprend un index.</note>
  <note>Comprend des réf. bibliogr.</note>
  <note>Comprend un index.</note>
  <subject authority="rvm">
    <topic>Réseaux logiques programmables par l'utilisateur</topic>
  </subject>
  <subject authority="lcsh">
    <topic>Field programmable gate arrays</topic>
  </subject>
  <subject>
    <topic>Matrices de puertas programables</topic>
  </subject>
  <subject>
    <topic>Primera Jornada de Catalogacion</topic>
  </subject>
  <subject>
    <topic>Application</topic>
    <topic>Architecture</topic>
    <topic>Circuit</topic>
    <topic>Fpga</topic>
    <topic>Integre</topic>
    <topic>Logique</topic>
    <topic>Matrice</topic>
    <topic>Porte</topic>
    <topic>Programmable</topic>
    <topic>Reseau</topic>
  </subject>
  <subject>
    <topic>Utilisateur</topic>
    <topic>Specifique</topic>
    <topic>Numerique</topic>
  </subject>
  <classification authority="lcc">TK 7895 M463d 2004</classification>
  <classification authority="ddc">621.39</classification>
  <identifier type="isbn">0750676043</identifier>
  <identifier type="isbn">9780750676045</identifier>
  <identifier type="lccn">2004557408</identifier>
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